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A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

ELKHOLY-DISSERTATION-2016-adpll

ELKHOLY-DISSERTAT[..]

SARADC设计

SARADC设计

计算电磁学 by 王秉中,邵维 (z-lib.org)

计算电磁学 by 王秉中,邵维 (z-lib.org)

NoiseDesign.dvi

NoiseDesign.dvi

一种低压CMOSLDO稳压电源电路

一种低压CMOSLDO稳压电源电路

CMOS带隙基准源研究现状幸新鹏

CMOS带隙基准源研究现状幸新鹏

A Low Power Two Stages CMOS OpAmp

A Low Power Two Stages CMOS OpAmp

Understanding Jitter Requirements of PLL-Based Processors Application Note (EE-261)

Understanding Jitter Requirements of PLL-Based Processors Application ...

ANALOG DEVICES INC.

The advanced part of A treatise on the dynamics of a system of rigid bodies. Being part II of a treatise on the whole subject. With numerous examples. By Edward John Routh.

The advanced part of A treatise on the dynamics of a system ...

Routh, Edward John, 1831-1907.

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

Signal and Power Integrity - Simplified, Third edition

Signal and Power Integrity - Simplified, Third edition

基于ac620的fpga系统设计与验证实战指南20190516

基于ac620的fpga系统设计与[..]

高精度sigma-delta ADC设计研究与实现

高精度sigma-delta ADC设计研究与实现

带隙基准电路的研究

带隙基准电路的研究

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

线性代数教材(同济五版+学习辅导与习题全解)

线性代数教材(同济五版+学习辅导与[..]

EDA与IC设计 CMOS集成电路后端设计与实战

EDA与IC设计 CMOS集成电路后端设计与实战

Category: 2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB);2016; ; ;10.1109/ICUWB.2016.7790413

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li