两种新型CMOS带隙基准电路 程军
CNKI
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
未知
Solution-for-Design of Analog CMOS Integrated Circuits 2nd
带隙基准电路的研究
<CCC6B3A4CEC4>
CMOS带隙基准源研究与设计
dwd
Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS
An improved bandgap reference with high power supply rejection ...
模拟CMOS集成电路设计
Behzad.Razavi（第2版 ）（中文 ）hd R2A修复版本2023-11-08
基于运算放大器和模拟集成电路的电路[..] with Operational Amplifiers and Analog ...
Sergio Franco 著
CMOS高性能运算放大器研究与设计
0132642786.pdf
Neil H. E. Weste
Session 4
PLL 设计仿真及应用
Roland E. Best
CN104391533A-High[..] (power supply rejection ratio) LDO (low ...
PrimeSim� HSPICE® User Guide: Advanced Analog Simulation and ...
Inc. Synopsys
模拟集成电路分析与设计 洪志良
CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学)
FREQUENCY DIVIDINGAPPARATUS AND RELATED METHOD
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...