理工书库 lilin | Category: The specific processor that we analyze here is ADSP-TS201S from TigerSHARC® family of processors. Some of the subjects discussed here will apply to jitter in general

Discover (Random Books)

CMOS Analog Circuit Design (1)

CMOS Analog Circuit Design (1)

集成电路版图设计 [陆学斌主编] 2012年版

集成电路版图设计 [陆学斌主编] 2012年版

高数第七版下册

高数第七版下册

Switching Power Supplies A to Z

Switching Power Supplies A to Z

Sanjaya_Maniktala

ISSCC 2019 Digest of Technical Papers

ISSCC 2019 Digest of Technical Papers

JSSC 202212

JSSC 202212

带ESD保护结构的IO单元库的设计

带ESD保护结构的IO单元库的设计

锁相环(PLL)电路设计与应用

锁相环(PLL)电路设计与应用

(日)远坂俊昭著何希才译

jssc.2005.Replica Compensated Linear Regulators for PLLs

jssc.2005.Replica Compensated Linear Regulators for PLLs

examples

examples

模拟CMOS集成电路设计

模拟CMOS集成电路设计

Behzad.Razavi（第2版）（中文）hd R2A修复版本2023-11-08

Microsoft Word - AXI protocol 翻译.doc

Microsoft Word - AXI protocol 翻译.doc

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li

All-Digital Frequency Synthesizer for RF Wireless Application

All-Digital Frequency Synthesizer for RF Wireless Application

AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite

AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ...

Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double - Proceedings of the IEEE

Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: ...

MATLAB-SIMULINK通信系统建模与仿真实例分析-清华大学 2

MATLAB-SIMULINK通信[..] 2

柯明道ESD简洁版

柯明道ESD简洁版

Category: The specific processor that we analyze here is ADSP-TS201S from TigerSHARC® family of processors. Some of the subjects discussed here will apply to jitter in general

Understanding Jitter Requirements of PLL-Based Processors Application Note (EE-261)

Understanding Jitter Requirements of PLL-Based Processors Application ...

ANALOG DEVICES INC.