CMOS Fractional-N Synthesizers: Design for High Spectral Purity ...
Bram De Muer & Michiel Steyaert
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
Session 31
未知
Static Timing Analysis final
一种快速瞬态响应的无片外电容LDO[..]
ISSCC2021-T8-On-Chip Interconnects Basic Concepts, Designs, ...
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...
CMOS Realization of OTA as an Application in Low Power Amplifier ...
Ghanshyam Singh, Md Hameed Pasha
Silicon-Germanium Heterojunction Bipolar Transistors (2002)
ESD in Silicon Integrated Circuits
信号与系统下 第三版
Preparation of Papers in Two-Column Format for the Proceedings ...
Laura Hyslop
一种应用于LDO的高性能过温保护电路设计
FinFET Modeling for IC Simulation and Design
4<8=8AB@0B>@
ADS射频电路设计与仿真从入门到精通
陈铖颖
功率谱密度计算
yzx
Microsoft Word - 异步FIFO的设计.doc
Jerry
MT-001: Taking the Mystery out of the Infamous Formula,'SNR ...
Walt Kester
Understanding Jitter Requirements of PLL-Based Processors Application ...
ANALOG DEVICES INC.