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Discover (Random Books)

Cadence PVS Developers Guide

Cadence PVS Developers Guide

Inc. Cadence Design Sys tems

Verilog数字VLSI设计教程

Verilog数字VLSI设计教程

【作 者】李林编著

jssc.2005.Replica Compensated Linear Regulators for PLLs

jssc.2005.Replica Compensated Linear Regulators for PLLs

未知

Computing the continuous discretely. Integer-point enumeration in polyhedra Beck, Matthias Robins, Sinai (z-lib.org)

Computing the continuous discretely. Integer-point enumeration ...

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sido buck converter

sido buck converter

Duyu Liu & Xinzhi Liu & Hao Chen & Shouming Zhong

精通开关电源设计(第2版)

精通开关电源设计(第2版)

未知

Advanced Electromagnetic Computation

Advanced Electromagnetic Computation

Dikshitulu K. Kalluri

bingdian001.com

bingdian001.com

bingdian001.com

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

未知

Virtuoso Parameterized Cell Reference

Virtuoso Parameterized Cell Reference

Inc. Cadence Design Sys tems

Memory systems_ cache, DRAM, disk -- Bruce Jacob, Spencer Ng, David Wang -- 2008 -- Morgan-Kaufmann -- 9780080553849 -- 744cd27339b303e7e5478e7cfaa15fb1 -- Anna’s Archive

Memory systems_ cache, DRAM, disk -- Bruce Jacob, Spencer Ng, ...

未知

基于CMOS工艺的全芯片ESD保护电路设计

基于CMOS工艺的全芯片ESD保护[..]

未知

Spectre Circuit Simulator Reference

Spectre Circuit Simulator Reference

Inc. Cadence Design Sys tems

Spice Modeling and Simulation of a MPPT Algorithm

Spice Modeling and Simulation of a MPPT Algorithm

未知

A simple three-terminal IC bandgap reference

A simple three-terminal IC bandgap reference

A.P. Brokaw

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N ...

Bo Zhou & Yao Li & Fuyuan Zhao

一种适用于DDR内存驱动的LDO芯片设计

一种适用于DDR内存驱动的LDO芯片设计

未知

Digital Logic and Computer Design

Digital Logic and Computer Design

M. MORRIS MANO

Category: 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512);2004;1; ;10.1109/ISCAS.2004.1328296

Design of class AB output stages using the structural methodology

Design of class AB output stages using the structural methodology

V. Ivanov & I. Filanovsky

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