JSSC 202212
未知
低功耗的高速高精度运放设计
HarmonicBalance
一种自适应补偿的宽输入LDO设计
Microsoft Word - xx3_apx_ce.doc
Rashaunda Henderson
CMOS IC LAYOUT
Wei Zhi
Session 10: Continuous-Time ADCs and DACs
CMOS电路芯片ESD保护电路设计[..] 赵近
ARM AMBA 5 AHB Protocol Specification AHB5, AHB-Lite
ARM Limited
Spectre Classic Simula tor, Spectre APS, Spectre X, Spectre ...
Inc. Cadence Design Sys tems
一种加入动态补偿电路的快速响应LDO设计
Altera系列FPGA芯片IP核详解
ISSCC2020-01 Visuals
Steve Bonney
MCU芯片的复位电路与多模式时钟系统设计
周小军
Creating Qsys Components
Altera Corporation
高速低功耗SAR ADC的关键技术研究与系统设计
HKF
有限元方法（第五版）第一卷 基本原理
（英）O.C.Zienkiewicz （美）R.L.Taylor著
93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Teleco[..] ...
LAN/MAN Standards Committee of the IEEE Computer Society
IEEE Std 802.11b-1999
IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition ...
An improved bandgap reference with high power supply rejection ...
Instruction for Camera-Ready Paper
Guo-Ping Ru
Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...
Intel Corporation
Intel® Quartus® Prime Standard Edition User Guide Platform Designer
Internal and external op-amp compensation: a control-centric ...
Introduction to advance node feathers
88691
Introduction to AMBA Bus System
吳欣龍
Introduction to Linear Algebra by Gilbert Strang (z-lib.org)
Introduction to RF Power Amplifier Design and Simulation (Abdullah ...
Introduction to RF Simulation and its Application
Ken Kundert
introduction.ppt
kdjwang
Introductory Circuit Analysis Thirteenth Edition Global Edition
Robert L. Boylestad
IP3 and Intermodulation Guide | Maxim Integrated
ISF_TUTORIAL
YIZHE HU
ISM-PLL
ISSC2021 SESSION 2
ISSCC 2019 Digest of Technical Papers
ISSCC2017-24 Visuals(2)
ISSCC2020-01 Digest
ISSCC2021 Session 15
ISSCC2021 Session 17
ISSCC2021 Session 21
ISSCC2021 Session 23
ISSCC2021 Session 27
ISSCC2021 Session 28
ISSCC2021 Session 29
ISSCC2021-1 3
ISSCC2021-SC1
ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
ISSCC2021-SC2
ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...
ISSCC2021-SC3
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
ISSCC2021-SC4
ISSCC2021-SC4-Pro[..] Clock Generation, Distribution, and Clock ...
ISSCC2021-T1-Fund[..] of RF and Mm-Wave Power Amplifier Designs
ISSCC2021-T10-Fun[..] of Fully-Integrated Voltage Regulators
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design
ISSCC2021-T12-com[..]
ISSCC2021-T2-Fund[..] of Memory Subsystem Design for HPC and ...
ISSCC2021-T3-Silicon Photonics – from Basics to ASICs
ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...
ISSCC2021-T5-Cali[..] Techniques in ADCs
ISSCC2021-T6-Basics of DAC-based Wireline Transmitters
ISSCC2021-T7-Basic Design Approaches to Accelerating Deep Neural ...
ISSCC2021-T8-On-Chip Interconnects Basic Concepts, Designs, ...
ISSCC2021-T9-Desi[..] Amplifiers for Stability
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx, Inc.
Jespers-The gm ID Methodology, a sizing tool
jrproc.1950.Bothw[..] F.E.-Nyquist Diagrams and the Routh-Hurwitz ...
js.2010.PFD biased with shunt regulator
jssc.2005.Replica Compensated Linear Regulators for PLLs
Julia中文文档
Katsuhiko Ogata
dynstab2/ThePirateBay