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A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai

RISC-V IOMMU Architecture Specification

RISC-V IOMMU Architecture Specification

IOMMU Task Group

thesis.dvi

thesis.dvi

单片射频微波集成电路技术与设计 (文光俊) (Z-Library)

单片射频微波集成电路技术与设计 (文光俊) (Z-Library)

Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional-<formula formulatype="inline"><tex Notation="TeX">$N$</tex> </formula> PLLs

Analytical Phase-Noise Modeling and Charge Pump Optimization ...

Frank Herzel;Sabbir A. Osmany;J. Christoph Scheytt

CMOS Mix-Signal Circuit Design Baker

CMOS Mix-Signal Circuit Design Baker

A comparative study of various current mirror configurations_ Topologies and characteristics

A comparative study of various current mirror configurations_ ...

Bhawna Aggarwal & Maneesha Gupta & A.K. Gupta

Theory of Modeling and Simulation (Bernard P. Zeigler, Alexandre Muzy etc.) (Z-Library)

Theory of Modeling and Simulation (Bernard P. Zeigler, Alexandre ...

Bernard P. Zeigler

Single miller capacitor frequency compensation technique for low power multistage amplifiers

Single miller capacitor frequency compensation technique for ...

托马斯微积分

托马斯微积分

（美）芬尼（美）韦尔（美）焦尔当诺著叶其孝王耀东唐兢译

FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard (Yogesh Singh Chauhan, Darsen Duane Lu etc.) (Z-Library)

FinFET Modeling for IC Simulation and Design Using the BSIM-CMG ...

Modelling Methodologies in Analogue Integrated Circuit Design

Modelling Methodologies in Analogue Integrated Circuit Design

Günhan Dündar & Mustafa Berke Yelten (Editors)

Presentation

Presentation

509764_1_En_Print.indd

509764_1_En_Print[..]

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication

Distributed Loss-Compensation Techniques for Energy-Efficient ...

Electronic Circuits with MATLAB, PSpice, and Smith Chart (Won Y. Yang, Jaekwon Kim, Kyung W. Park etc.) (Z-Library)

Electronic Circuits with MATLAB, PSpice, and Smith Chart (Won ...

概率论与数理统计教程第三版 (茆诗松) (Z-Library)

概率论与数理统计教程第三版 (茆诗松) (Z-Library)

Books

Pages from M.E. Van Valkenburg - Network Analysis 6(1959, Prentice Hall, Inc)

Pages from M.E. Van Valkenburg - Network Analysis 6(1959, Prentice ...

S_Para_E.PM6

S_Para_E.PM6

Understanding Phase Noise in LC VCOs

Understanding Phase Noise in LC VCOs

A Key Problem in RF Integrated Circuits

相位噪声、通行链路预算

相位噪声、通行链路预算

Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS

Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS

二级密勒补偿运算放大器

二级密勒补偿运算放大器

LDO设计-tangzhangwen

LDO设计-tangzhangwen

OPAMP设计-tangzhangwen

OPAMP设计-tangzhangwen

全差分运算放大器设计-tangzhangwen

全差分运算放大器设计-tangzh[..]

CMOS 带隙基准源研究-tangzhangwen

CMOS 带隙基准源研究-tangzhangwen

基准源和温度检测模块设计-tangzhangwen

基准源和温度检测模块设计-tang[..]

基准电压源和线性稳压器的设计-tangzhangwen

基准电压源和线性稳压器的设计-ta[..]

Analog Behavioral Modeling with the Verilog-A Language

Analog Behavioral Modeling with the Verilog-A Language

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

学校代码： 10246

学校代码： 10246

The Delta-Sigma Modulator [A Circuit for All Seasons]

The Delta-Sigma Modulator [A Circuit for All Seasons]

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N ...

Bo Zhou & Yao Li & Fuyuan Zhao

HJ-MASH 多模多标准CMOS锁相环频率综合器中小数分频器的设计史鹏鹏

HJ-MASH 多模多标准CMOS锁相环频率综合器[..] 史鹏鹏

ELKHOLY-DISSERTATION-2016-adpll

ELKHOLY-DISSERTAT[..]

CN106656160A-上海集成电路研发中心2017-优化占空比的高速电平转换电路

CN106656160A-上海集成[..]

CN101969305B-威盛电子2012-Potential conversion circuit

CN101969305B-威盛电子[..] conversion circuit

CN101140511B-硅谷数模2010-Cascaded carry binary adder

CN101140511B-硅谷数模[..] carry binary adder

哈尔滨工业大学硕士毕业论文模板

哈尔滨工业大学硕士毕业论文模板

在线作Bode/Nyquis

在线作Bode/Nyquis

jrproc.1950.Bothwell, F.E.-Nyquist Diagrams and the Routh-Hurwitz Stability Criterion

jrproc.1950.Bothw[..] F.E.-Nyquist Diagrams and the Routh-Hurwitz ...

The advanced part of A treatise on the dynamics of a system of rigid bodies. Being part II of a treatise on the whole subject. With numerous examples. By Edward John Routh.

The advanced part of A treatise on the dynamics of a system ...

Routh, Edward John, 1831-1907.

bstj.1932.Nyquist, H.-Regeneration Theory

bstj.1932.Nyquist, H.-Regeneration Theory

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin

Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) (Z-Library)

Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...

Sigma-Delta Converters Practical Design Guide, 2nd Edition

Sigma-Delta Converters Practical Design Guide, 2nd Edition

一种基于广义时间和传递常数的快速分析法郑立博

一种基于广义时间和传递常数的快速分析法郑立博

Design of Sigma-Delta Converters in MATLAB-

Design of Sigma-Delta Converters in MATLAB-

Dynamic Analysis of Switching-Mode DC DC Converters-Springer Netherlands (1991)

Dynamic Analysis of Switching-Mode DC DC Converters-Springer ...

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application

A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A<sup>2</sup>-Comparator and Sleep-Time Detector for IoT Application

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...

Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell lib - Solid-State Circuits, IEEE Journal of

A compact power-efficient 3 V CMOS rail-to-rail input/output ...

模拟CMOS集成电路第二版拉扎维 (拉扎维)

模拟CMOS集成电路第二版拉扎维 (拉扎维)

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

Distributed MOS varactor biasing for VCO gain equalization in ...

J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval

Power systems-on-chip practical aspects of design (Allard, Bruno) (Z-Library)

Power systems-on-chip practical aspects of design (Allard, Bruno) ...

运算放大器理论与设计 9影印版（荷）惠意欣著

运算放大器理论与设计 9影印版（荷）惠意欣著

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai

低电压、低功耗助听器电路系统芯片研究

低电压、低功耗助听器电路系统芯片研究

低中频接收机中复数滤波器的设计

低中频接收机中复数滤波器的设计

ZigBee低中频接收机中复数滤波器的设计

ZigBee低中频接收机中复数滤波[..]

GPS接收机内带镜像抑制的中频滤波器设计

GPS接收机内带镜像抑制的中频滤波器设计

用于OFDM+UWB系统中的中频滤波器和可变增益放大器的研究设计

用于OFDM+UWB系统中的中频滤[..]

射频接收机中模拟信道滤波器设计

射频接收机中模拟信道滤波器设计

射频系统内低中频滤波器的设计和研究

射频系统内低中频滤波器的设计和研究

射频集成电路中模拟基带滤波器的设计和实现石欢

射频集成电路中模拟基带滤波器的设计和实现石欢

25Gbps系统封装和高速互连的信号完整性的基础性研究

25Gbps系统封装和高速互连的信[..]

高频高速电子系统中的信号完整性研究

高频高速电子系统中的信号完整性研究

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...

Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao

Signal and Power Integrity - Simplified, Third edition

Signal and Power Integrity - Simplified, Third edition

A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes

A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...

Chethan Rao & Alvin Wang & Shaishav Desai

学校代码 10530 学号 201110061316

学校代码 10530 学号 201110061316

高速信令-抖动建模-分析预算

高速信令-抖动建模-分析预算

高速数字电路设计中信号完整性分析与研究

高速数字电路设计中信号完整性分析与研究

2.7Gbps收发器中LVDS驱动电路的设计

2.7Gbps收发器中LVDS驱动[..]

带ESD保护结构的IO单元库的设计

带ESD保护结构的IO单元库的设计