MIPI高速数据接口的研究与实现
未知
半导体器件物理(原书第三版)中文版[..]
Session 3
Computational electromagnetism variational formulations, complementarity, ...
Analysis and Design of Transimpedance Amplifiers for Optical ...
4<8=8AB@0B>@
Session 15: Compute-in-Memory Processors for Deep Neural Networks
An improved bandgap reference with high power supply rejection ...
Millimeter-Wave Frequency Reconfigurable Dual-Band CMOS Power ...
Jaehun Lee & Ji-Seon Paek & Songcheol Hong
ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...
IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...
Design Automation Standards Committee of the IEEE Computer Society
HJ-MASH 多模多标准CMOS锁相环频率综合器[..] 史鹏鹏
Jish
华侨大学模拟IC实验8 无缓冲两级运放设计
USER
Sweetspot
Design of Low Noise Amplifiers
Steve Long
一种带软启动电路的带隙基准电压源的实现 张科
CNKI
学校代码 10530 学 号 201110061316
zxsr70885
CMOS-Voltage-Refe[..]
RF ANALOG IC DESIGN PROJECT
ctao
高性能流水线模数转换器及其数字校准[..] 贾华宇
12bit pipeline ADC design
应用于流水线ADC的比较器的设计与研究
高速模数转换器动态参数的定义和测试
比较器失调的仿真方法
jason
1.5Bit 级pipelined+ADC典型单[..]
12位50Msps流水线A D转换器的研究与设计
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
16位高速CMOS流水线模数转换器[..] (1)
基于功耗优化的Pipelined+[..] (1)
适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
参考书 芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立
模拟集成电路信号完整性中抖动与振铃[..]
USB 3.0中五分频电路设计
TOM
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
CN105763219A-2016[..]
基于自偏置技术的锁相环设计 刘克赛2019
刘克赛
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
Noise and Spurious Tones Management Techniques for Multi-GHz ...
Adrian Maxim
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi
Oscillator phase noise: a tutorial
T.H. Lee;A. Hajimiri
All-Digital Frequency Synthesizer for RF Wireless Application
tcheng
相位噪声jitter基本定义
yzx
锁相环相位噪声与环路带宽的关系分析
Wiener-Khinchin theorem
2004Beek
锁相环型频率综合器中的高速分频器 袁泉
High-Speed Architecture for a Programmable Frequency Divider ...
IEEE
系统芯片中的全数字锁相环设计
A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...
Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang
基于 DLL倍频技术的 1GHz本地振荡器设计 英文 李金城
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...
14990665645773625[..]
DELAY LOCKLOOP CIRCUIT
DUTY CYCLE CORRECTION CIRCUITRY
ISM-PLL
共源共栅实验五
工作在亚阈值区CMOS OTA的研究
反馈运算放大器电路的噪声分析和设计
Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...
一款轨到轨输入 输出运算放大器的设计与研究 辛国松
Matching Analysis and the Design of Low Offset Amplifiers
补偿电路总结
番茄花园
频率补偿研究心得
Modified modeling of Miller compensation for two-stage operational ...
H.C. Yang;D.J. Allstot
一个全差分运放电路的设计
Administrator
The Biquadratic Filter [A Circuit for All Seasons]
Behzad Razavi
Distributed Loss-Compensation Techniques for Energy-Efficient ...
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
K. Bult;G.J.G.M. Geelen
Internal and external op-amp compensation: a control-centric ...
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
MOSAmpNoise.dvi
NoiseDesign.dvi
Design techniques for cascoded CMOS op amps with improved PSRR ...
D.B. Ribner & M.A. Copeland