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Practical MATLAB Modeling with Simulink Programming and Simulating Ordinary and Partial Differential Equations (Sulaymon L. Eshkabilov) (Z-Library)

Practical MATLAB Modeling with Simulink Programming and Simulating ...

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

mssc.2015.Razavi-The StrongARM Latch

mssc.2015.Razavi-The StrongARM Latch

一种低温漂CMOS带隙基准电压源的设计陈碧

一种低温漂CMOS带隙基准电压源的设计陈碧

IC Mask Design

IC Mask Design

Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science) (Cicero S. Vaucher) (Z-Library)

Architectures for RF Frequency Synthesizers (The Springer International ...

BSIM4 AND MOSFET MODELING FOR IC SIMULATION

BSIM4 AND MOSFET MODELING FOR IC SIMULATION

Hu, Chenming, Liu, Weidong

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离散时间信号处理（第三版） ([美]奥本海姆) (Z-Library) (1)

离散时间信号处理（第三版） ([美]奥本海姆) (Z-Library) (1)

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...

高速数字电路设计中信号完整性分析与研究

高速数字电路设计中信号完整性分析与研究

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

高频高速电子系统中的信号完整性研究

高频高速电子系统中的信号完整性研究

Operation and Modeling of the MOS Transistor By Tsividis

Operation and Modeling of the MOS Transistor By Tsividis

MCU芯片的复位电路与多模式时钟系统设计

MCU芯片的复位电路与多模式时钟系统设计

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang

CN105824349A-上海巨微集成-chopped bandgap

CN105824349A-上海巨微[..] bandgap

Books

A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With Integrated Low-Power Oscillator- Driven Charge-Pump and Switched-Capacitor Pole Tracking Compensation

A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...

Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar

一种具有温度补偿高电源抑制比的带隙基准源何捷

一种具有温度补偿高电源抑制比的带隙基准源何捷

一种高性能CMOS带隙电压基准源设计朱樟明

一种高性能CMOS带隙电压基准源设计朱樟明

简并点优化的高性能带隙基准电路

简并点优化的高性能带隙基准电路

工作于亚阈值区的偏置基准电路-峰值电流镜

工作于亚阈值区的偏置基准电路-峰值电流镜

高精度带隙基准电压源的研究与设计

高精度带隙基准电压源的研究与设计

电源芯片中CMOS带隙基准源与微调的设计与实现 (1)

电源芯片中CMOS带隙基准源与微调[..] (1)

Low-Cost Low-Power 2.4 GHz RF Transceiver datasheet (Rev. C)

Low-Cost Low-Power 2.4 GHz RF Transceiver datasheet (Rev. C)

Texas Instruments, Incorporated [SWRS040,C

Nested Miller compensation in low-power CMOS design

Nested Miller compensation in low-power CMOS design

Ka Nang Leung;P.K.T. Mok

RC OSCILLATOR WITH ADDITIONAL NVERTER IN SERIES WITH CAPACTOR

RC OSCILLATOR WITH ADDITIONAL NVERTER IN SERIES WITH CAPACTOR

高精度sigma-delta ADC设计研究与实现

高精度sigma-delta ADC设计研究与实现

一种具有采样保持功能的开关电容积分器宋文清

一种具有采样保持功能的开关电容积分器宋文清

基于Latch的CMOS动态比较器的研究

基于Latch的CMOS动态比较器的研究

低压、低功耗、高精度的逐次逼近型

低压、低功耗、高精度的逐次逼近型

Advanced data converters G Manganaro

Advanced data converters G Manganaro

e采样与adc

e采样与adc

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR - Solid-State Circuits, IEEE Journal of

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...

Abidi-Pan, Hui.University of California, Los Angeles

Abidi-Pan, Hui.University of California, Los Angeles

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

SAR A／D转换器中电容失配问题的分析

SAR A／D转换器中电容失配问题的分析

RF Sampling for Multi-band Radios

RF Sampling for Multi-band Radios

Texas Instruments, Incorporated [SBAA328,*]

CMOS Sigma-Delta Converters Practical Design Guide

CMOS Sigma-Delta Converters Practical Design Guide

高性能流水线模数转换器及其数字校准技术研究贾华宇

高性能流水线模数转换器及其数字校准[..] 贾华宇

12bit pipeline ADC design

12bit pipeline ADC design

应用于流水线ADC的比较器的设计与研究

应用于流水线ADC的比较器的设计与研究

高速模数转换器动态参数的定义和测试

高速模数转换器动态参数的定义和测试

比较器失调的仿真方法

比较器失调的仿真方法

1.5Bit 级pipelined+ADC典型单级电路结构实现研究

1.5Bit 级pipelined+ADC典型单[..]

12位50Msps流水线A D转换器的研究与设计

12位50Msps流水线A D转换器的研究与设计

Sampled Systems and the Effects of Clock Phase Noise and Jitter Application Note (AN-756)

Sampled Systems and the Effects of Clock Phase Noise and Jitter ...

Analog Devices, Inc.

16位高速CMOS流水线模数转换器关键技术研究 (1)

16位高速CMOS流水线模数转换器[..] (1)

基于功耗优化的Pipelined+ADC系统结构设计与关键单元研究 (1)

基于功耗优化的Pipelined+[..] (1)

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...

Rakesh H. Patel & William Bereza

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

模拟集成电路信号完整性中抖动与振铃问题的研究

模拟集成电路信号完整性中抖动与振铃[..]

USB 3.0中五分频电路设计

USB 3.0中五分频电路设计

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...

Cheng-Ru Ho & Mike Shuo-Wei Chen

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...

Shih-An Yu & Peter R. Kinget

CN105763219A-2016-一种占空比为25%的分频器

CN105763219A-2016[..]

基于自偏置技术的锁相环设计刘克赛2019

基于自偏置技术的锁相环设计刘克赛2019

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...

Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly

LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References Cited DETECTING METHOD

LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...

Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs

Noise and Spurious Tones Management Techniques for Multi-GHz ...

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN PHY

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi

Oscillator phase noise: a tutorial

Oscillator phase noise: a tutorial

T.H. Lee;A. Hajimiri

All-Digital Frequency Synthesizer for RF Wireless Application

All-Digital Frequency Synthesizer for RF Wireless Application

相位噪声jitter基本定义

相位噪声jitter基本定义

锁相环相位噪声与环路带宽的关系分析

锁相环相位噪声与环路带宽的关系分析

Wiener-Khinchin theorem

Wiener-Khinchin theorem

2004Beek

2004Beek

锁相环型频率综合器中的高速分频器袁泉

锁相环型频率综合器中的高速分频器袁泉

High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler - Solid-State Circuits, IEEE Journal of

High-Speed Architecture for a Programmable Frequency Divider ...

系统芯片中的全数字锁相环设计

系统芯片中的全数字锁相环设计

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques [Paper] - Solid-State Circuits, IEEE Journal of

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...

1499066564577362562-06963235

14990665645773625[..]