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7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge (XAPP1286)

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...

模拟集成电路设计精粹——Analog Design Essentials

模拟集成电路设计精粹——Analog Design Essentials

Willy M.C. Sansen 著 & 陈莹梅译 & 王志功审校

Computational Electromagnetics with MATLAB®, Fourth Edition

Computational Electromagnetics with MATLAB®, Fourth Edition

Matthew N.O. Sadiku

Silicon-Germanium Heterojunction Bipolar Transistors (2002)

Silicon-Germanium Heterojunction Bipolar Transistors (2002)

The Method of Moments in Electromagnetics, Second Edition

The Method of Moments in Electromagnetics, Second Edition

Gibson, Walton C.

射频集成电路与系统

射频集成电路与系统

李智群王志功编著

Low-Cost Low-Power 2.4 GHz RF Transceiver datasheet (Rev. C)

Low-Cost Low-Power 2.4 GHz RF Transceiver datasheet (Rev. C)

Texas Instruments, Incorporated [SWRS040,C

高速低功耗逐次逼近型模数转换器的研究与设计

高速低功耗逐次逼近型模数转换器的研[..]

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...

模拟集成电路分析与设计

模拟集成电路分析与设计

Session 32: Frequency Synthesizers

Session 32: Frequency Synthesizers

Design of an Active Harmonic Rejection N-Path Filter for Highly T

Design of an Active Harmonic Rejection N-Path Filter for Highly ...

Caleb Mosby Munsill

0071509054.pdf

0071509054.pdf

模拟集成电路信号完整性中抖动与振铃问题的研究

模拟集成电路信号完整性中抖动与振铃[..]

CMOS模拟集成电路3艾伦-英文版

CMOS模拟集成电路3艾伦-英文版

Ring PLL的详细设计博士论文

Ring PLL的详细设计博士论文

硕士论文-宽带匹配网络的实频法研究

硕士论文-宽带匹配网络的实频法研究

Session 8: Ultra-High-Speed Wireline

Session 8: Ultra-High-Speed Wireline

Books

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi

Oscillator phase noise: a tutorial

Oscillator phase noise: a tutorial

T.H. Lee;A. Hajimiri

All-Digital Frequency Synthesizer for RF Wireless Application

All-Digital Frequency Synthesizer for RF Wireless Application

相位噪声jitter基本定义

相位噪声jitter基本定义

锁相环相位噪声与环路带宽的关系分析

锁相环相位噪声与环路带宽的关系分析

Wiener-Khinchin theorem

Wiener-Khinchin theorem

2004Beek

2004Beek

锁相环型频率综合器中的高速分频器袁泉

锁相环型频率综合器中的高速分频器袁泉

High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler - Solid-State Circuits, IEEE Journal of

High-Speed Architecture for a Programmable Frequency Divider ...

系统芯片中的全数字锁相环设计

系统芯片中的全数字锁相环设计

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques [Paper] - Solid-State Circuits, IEEE Journal of

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...

1499066564577362562-06963235

14990665645773625[..]

DELAY LOCKLOOP CIRCUIT

DELAY LOCKLOOP CIRCUIT

DUTY CYCLE CORRECTION CIRCUITRY

DUTY CYCLE CORRECTION CIRCUITRY

ISM-PLL

ISM-PLL

共源共栅实验五

共源共栅实验五

工作在亚阈值区CMOS OTA的研究

工作在亚阈值区CMOS OTA的研究

反馈运算放大器电路的噪声分析和设计

反馈运算放大器电路的噪声分析和设计

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...

一款轨到轨输入输出运算放大器的设计与研究辛国松

一款轨到轨输入输出运算放大器的设计与研究辛国松

Matching Analysis and the Design of Low Offset Amplifiers

Matching Analysis and the Design of Low Offset Amplifiers

补偿电路总结

补偿电路总结

频率补偿研究心得

频率补偿研究心得

Modified modeling of Miller compensation for two-stage operational amplifiers

Modified modeling of Miller compensation for two-stage operational ...

H.C. Yang;D.J. Allstot

一个全差分运放电路的设计

一个全差分运放电路的设计

The Biquadratic Filter [A Circuit for All Seasons]

The Biquadratic Filter [A Circuit for All Seasons]

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication

Distributed Loss-Compensation Techniques for Energy-Efficient ...

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

K. Bult;G.J.G.M. Geelen

Internal and external op-amp compensation: a control-centric tutorial - American Control Conference, 2004. Proceedings of the 2004

Internal and external op-amp compensation: a control-centric ...

A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators

A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...

Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi

MIPI高速数据接口的研究与实现

MIPI高速数据接口的研究与实现

MOSAmpNoise.dvi

MOSAmpNoise.dvi

NoiseDesign.dvi

NoiseDesign.dvi

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Design techniques for cascoded CMOS op amps with improved PSRR ...

D.B. Ribner & M.A. Copeland

CMOS高性能运算放大器研究与设计

CMOS高性能运算放大器研究与设计

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...

模拟集成电路设计与仿真-何乐年

模拟集成电路设计与仿真-何乐年

FPGA 全芯片 ESD 防护设计和优化

FPGA 全芯片 ESD 防护设计和优化

CN104601160B-灿芯半导体2017-带ESD的高速输出级

CN104601160B-灿芯半导[..]

ESD Design and Synthesis (1)

ESD Design and Synthesis (1)

Abraham uta GPIO ESD

Abraham uta GPIO ESD

CMOS电路芯片ESD保护电路设计技术的发展赵近

CMOS电路芯片ESD保护电路设计[..] 赵近

A mixed-mode esd protection circuit simulation-design methodology - Solid-State Circuits, IEEE Journal of

A mixed-mode esd protection circuit simulation-design methodology ...

Virtuoso Editing 的使用简介

Virtuoso Editing 的使用简介

eetop.cn Matching

eetop.cn Matching

芯片I／O缓冲及ESD电路设计

芯片I／O缓冲及ESD电路设计

德州仪器高性能模拟器件高效应用指南之数据转换器_TI 大学计划

德州仪器高性能模拟器件高效应用指南[..] 大学计划

Texas Instruments, Incorporated [ZHCP055,*]

功率谱密度计算

功率谱密度计算

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

PoleZero.dvi

PoleZero.dvi

相位噪声、通行链路预算

相位噪声、通行链路预算

LDO设计-tangzhangwen

LDO设计-tangzhangwen

OPAMP设计-tangzhangwen

OPAMP设计-tangzhangwen

全差分运算放大器设计-tangzhangwen

全差分运算放大器设计-tangzh[..]

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

The Delta-Sigma Modulator [A Circuit for All Seasons]

The Delta-Sigma Modulator [A Circuit for All Seasons]

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget