Session 5
未知
一种快速瞬态响应的无片外电容LDO[..]
LDO中过温保护电路的设计
Session 9
普林斯顿概率论读本 (史蒂文．J．米勒 (Steven J. Miller)) (Z-Library)
Voltus-Fi Hierarchical IR Drop and EM Analysis
计算电磁学要论 by 盛新庆 (z-lib.org)
CNKI
<4D6963726F736F66[..]
linjie
基于自偏置技术的锁相环设计 刘克赛2019
刘克赛
深入理解LINUX网络技术内幕
CMOS Mixed-Signal Circuit Design, 2nd Ed
ISSCC2021-SC4-Pro[..] Clock Generation, Distribution, and Clock ...
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
K. Bult;G.J.G.M. Geelen
Design of Bandgap Reference and Current Reference Generator ...
Dracula Reference
Inc. Cadence Design Sys tems
高性能音频Delta-Sigma数[..]
All-Digital Frequency Synthesizer for RF Wireless Application
tcheng
集成稳压电路系统鲁棒性与快速响应研究
PLL WITH LOW SPURS
MSSC.2016.B. Razavi-TSPC Logic
Noise and Spurious Tones Management Techniques for Multi-GHz ...
Adrian Maxim
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
CN106357266B-华为20[..]
硅基压控振荡器的研究与设计 电子科技大学 彭羽
China
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
js.2010.PFD biased with shunt regulator
The Problem of PLL Power Consumption
Behzad Razavi
CN103036558B-SMIC[..]
ISSCC2021-SC4
ISSCC2021-SC2
ISSCC2021-SC1
ISSCC2021-SC3
CN105763219A-2016[..]
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
一种自参考结构的高速高精度片上时钟[..]
USB 3.0中五分频电路设计
TOM
模拟集成电路信号完整性中抖动与振铃[..]
参考书 芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭
基于功耗优化的Pipelined+[..] (1)
16位高速CMOS流水线模数转换器[..] (1)
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
AD9635 cn
12位50Msps流水线A D转换器的研究与设计
Aperture Uncertainty and ADC System Performance Application ...
MT-001: Taking the Mystery out of the Infamous Formula,'SNR ...
Walt Kester
1.5Bit 级pipelined+ADC典型单[..]
比较器失调的仿真方法
jason
高速模数转换器动态参数的定义和测试
适宜于系统集成的高速高精度模数转换[..]
应用于流水线ADC的比较器的设计与研究
12bit pipeline ADC design
高性能流水线模数转换器及其数字校准[..] 贾华宇
CMOS Sigma-Delta Converters Practical Design Guide
4<8=8AB@0B>@
通信标准对数据转换器的要求V1.0
RF Sampling for Multi-band Radios
Texas Instruments, Incorporated [SBAA328,*]
SAR A／D转换器中电容失配问题的分析
SAR ADC-MIT
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
Abidi-Pan, Hui.University of California, Los Angeles
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
IEEE
e采样与adc
Advanced data converters G Manganaro
HIGH SPEED AND LOW POWER DYNAMIC LATCH COMPARATOR
低压、低功耗、高精度的逐次逼近型
ycp
Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance ...
TrnoiseAN.fm
mtian
mssc.2015.Razavi-The StrongARM Latch
高速低功耗SAR ADC的关键技术研究与系统设计
HKF
基于Latch的CMOS动态比较器的研究
mssc.2015.The StrongARM Latch
一种具有采样保持功能的开关电容积分器 宋文清
高精度sigma-delta ADC设计研究与实现
Next-Generation ADCs, High-Performance Power Management, and ...