DjVu Document
Gustavo
Session 20
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一种极低静态电流LDO线性稳压器的设计
(EE) Razavi, Design of Analog CMOS Integrated Circuits 2nd
CN105824349A-上海巨微[..] bandgap
Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...
ISSCC2021 Session 29
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
lnaDesign2
Diva Reference
Inc. Cadence Design Sys tems
CMOS 集成电路设计手册 第3版·模拟电路篇=CMOS CIRCUIT DESIGN LAYOUT AND SIMULATION ...
Sahrling M. Analog Circuit Simulators for Integrated Circuit ...
Chap1_20160228_4.dvi
信号与系统 2nd 西蒙赫金
GmID Methodology
Administrator
Cancellation of Amplifier Offset and f-Noise An Improved Chopper ...
一种LDO使能控制端失效的分析方法
一种基于内部迟滞比较器的新型RC振荡器
Design of class AB output stages using the structural methodology
V. Ivanov & I. Filanovsky
Analysis and Design of ESD Protection for Robust Low-Power Pierce ...
Kim B. Ostman & Erlend Strandvik & Phil Corbishley & Tor Oyvind Vedal & Mika Salmi
A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...
Chethan Rao & Alvin Wang & Shaishav Desai
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...
Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li
A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...
Shih-An Yu & Peter R. Kinget
The Delta-Sigma Modulator [A Circuit for All Seasons]
Behzad Razavi
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
The Biquadratic Filter [A Circuit for All Seasons]
A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...
Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang
A modeling approach for /spl Sigma/-/spl Delta/ fractional-N ...
M.H. Perrott & M.D. Trott & C.G. Sodini
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...
Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar
Low Drop-Out Voltage Regulators: Capacitor-less Architecture ...
Joselyn Torres & Mohamed El-Nozahi & Ahmed Amer & Seenu Gopalraju & Reza Abdullah & Kamran Entesari & Edgar Sanchez-Sinencio
Digital Beamforming-Based Massive MIMO Transceiver for 5G Millimeter-Wave ...
Binqi Yang & Zhiqiang Yu & Ji Lan & Ruoqiao Zhang & Jianyi Zhou & Wei Hong
Frequency Reconfigurable mm-Wave Power Amplifier With Active ...
Chandrakanth R. Chappidi & Kaushik Sengupta
Millimeter-Wave Frequency Reconfigurable Dual-Band CMOS Power ...
Jaehun Lee & Ji-Seon Paek & Songcheol Hong
Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA ...
A Single-Trim CMOS Bandgap Reference With aInaccuracy of0.15% ...
Guang Ge & Cheng Zhang & Gian Hoogzaad & Kofi A. A. Makinwa
Design Procedure for Two-Stage CMOS Opamp using gm/ID design ...
Bakr Hesham & El-Sayed Hasaneen & Hesham F. A. Hamed
IEEE Standard for Ethernet