理工书库 lilin | Shelf: '锁相环 PLL DLL'

Shelf: '锁相环 PLL DLL'

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

[Behzad Razavi] Phase-Locking in High-Performance (BookFi)

[Behzad Razavi] Phase-Locking in High-Performance (BookFi)

全数字锁相环建模及分析代码-2014

全数字锁相环建模及分析代码-2014

COMS集成锁相环电路设计

COMS集成锁相环电路设计

Ring PLL的详细设计博士论文

Ring PLL的详细设计博士论文

COMS集成锁相环电路设计张刚

COMS集成锁相环电路设计张刚

锁相环(PLL)电路设计与应用

锁相环(PLL)电路设计与应用

(日)远坂俊昭著何希才译

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture ...

Phase Locked Loops for Wireless Communications

Phase Locked Loops for Wireless Communications

锁相环技术(第3版)——PhaseLock Techniques, Third Edition

锁相环技术(第3版)——Phase[..] Techniques, Third Edition

Floyd M. Gardner 著 & 姚剑清 & 译

PLL 设计仿真及应用

PLL 设计仿真及应用

ISSCC2021-SC1-Introduction to PLLs Phase Noise, Modeling, and Key Wireless Design Considerations

ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...

Modeling Jitter in PLL-based Frequency Synthesizers

Modeling Jitter in PLL-based Frequency Synthesizers

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application Considerations

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...

PLL WITH LOW SPURS

PLL WITH LOW SPURS

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS

基于自偏置技术的锁相环设计刘克赛2019

基于自偏置技术的锁相环设计刘克赛2019

HJ-MASH 多模多标准CMOS锁相环频率综合器中小数分频器的设计史鹏鹏

HJ-MASH 多模多标准CMOS锁相环频率综合器[..] 史鹏鹏

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques [Paper] - Solid-State Circuits, IEEE Journal of

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...

ISM-PLL

ISM-PLL

PLL频率合成器的杂散性能分析

PLL频率合成器的杂散性能分析

锁相环相位噪声与环路带宽的关系分析

锁相环相位噪声与环路带宽的关系分析

基于延迟锁相环的时钟发生器设计

基于延迟锁相环的时钟发生器设计

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

2019 Book Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

低电压CMOS分数分频锁相环频率综合器关键技术研究

低电压CMOS分数分频锁相环频率综合器关键技术研究

Microsoft PowerPoint - PLLnoise_jitter0209.ppt [相容模式]

Microsoft PowerPoint - PLLnoise_jitter02[..] [相容模式]

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N ...

Bo Zhou & Yao Li & Fuyuan Zhao